The present invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a method of forming a spacer on side and top portions of a photoresist pattern after a mask process so that the spacer may be used as an etching mask, thereby simplifying a spacer patterning technology (SPT) process.
Due to high-integration of semiconductor devices, the size and pitch of patterns for forming circuits is reduced. According to Rayleigh's equation, a size of a fine pattern in a semiconductor device is in proportion to a wavelength of light used in the exposure process and is in inverse proportion to a size of a lens in an exposer. Thus, methods for reducing the wavelength of light used in the exposure process or enlarging the size of the lens have been used to form fine patterns.
Various photo processes have overcome technical limits in the manufacture of semiconductor devices by the fine design of masks to adjust the amount of light transmitted through the mask, by the development of new photoresist materials, by the development of scanners using a high numerical aperture lens and by the development of a transformed mask.
However, it is difficult to form a desired width and pitch of patterns due to limits of exposure and resolution capacity using currently available light sources, e.g., KrF and ArF. For instance, exposure technologies to manufacture patterns of about 60 nm have been developed, but making patterns less than 60 nm becomes problematic.
Various studies have been conducted to form a photoresist pattern having a size and pitch of a fine pattern.
One of those studies is a double patterning technology (DPT) of performing double photo processes to form a pattern.
In one example of DPT, a double exposure etch technology (DE2T) includes exposing and etching a first pattern having a double cycle, and exposing and etching a second pattern having a double cycle between the first patterns. In another example of DPT, a spacer patterning technology (SPT) includes forming a pattern using a spacer.
Both the DE2T and the SPT may be performed with a negative tone and a positive tone.
In the negative tone DE2T, a pattern obtained from a first mask process is removed in a second mask process to form a desired pattern. In the positive tone DE2T, patterns obtained from a first mask process and a second mask process are combined to form a desired pattern.
The SPT is a self-aligned method that comprises performing a mask process once to pattern a cell region, thereby preventing mis-alignment.
However, in order to form a pad pattern in a core and peripheral circuit regions, an additional mask process is required to separate a pattern part of a mat edge region. Also, it is difficult to control deposition uniformity of a spacer forming region and regulate a critical dimension (CD) in a spacer etching process.
Although the SPT is singly applied to a NAND flash process in the case of a multi-layered structure including a line/space, a pattern cannot be formed by the SPT in the case of brick wall patterns of a DRAM and complicated pattern layers. In this case, the DE2T is required.